Case Studies
Physical Design Projects
Deep dives into RTL-to-GDSII implementations — problem, approach, sign-off metrics, and reports.
RISC-V Core — Full Physical Design
RTL-to-GDSII implementation of a 5-stage RV32I core in 45nm.
InnovusGenusPrimeTimeCalibre
Frequency
1.0 GHz
WNS
+0.02 ns
Case study
Low-Power AES-128 Accelerator
Power-aware floorplanning + multi-Vt for IoT-class encryption.
GenusInnovusPrimeTime PXVerilog
Power
41 µW
Throughput
1.28 Gbps
Case study
DDR4 PHY — Timing Closure
Sub-ps skew DLL + write-leveling on a 3200 MT/s PHY.
PrimeTimeInnovusHSPICE
Data Rate
3200 MT/s
Jitter
<18 ps
Case study