Case Studies
Physical Design Projects
Deep dives into RTL-to-GDSII implementations — problem, approach, sign-off metrics, and reports.
RISC-V Core — Full Physical Design
RTL-to-GDSII implementation of a 5-stage RV32I core in 45nm.
InnovusGenusPrimeTimeCalibre
Frequency
1.0 GHz
WNS
+0.02 ns
Case study
Low-Power AES-128 Accelerator
Power-aware floorplanning + multi-Vt for IoT-class encryption.
GenusInnovusPrimeTime PXVerilog
Power
41 µW
Throughput
1.28 Gbps
Case study
DDR4 PHY — Timing Closure
Sub-ps skew DLL + write-leveling on a 3200 MT/s PHY.
PrimeTimeInnovusHSPICE
Data Rate
3200 MT/s
Jitter
<18 ps
Case study
SHA256 Physical Design Implementation
Complete RTL-to-GDSII implementation of SHA256 in ASAP7nm.
Cadence InnovusASAP7nmTCL
Technology
ASAP7nm
Flow
RTL-to-GDSII
Case study
Automated 3D IC Compiler Flow for Simultaneous Timing Closure
Pseudo-3D physical design flow enabling timing-aware multi-tier implementation.
InnovusTempusTCLSDC
Flow Type
Pseudo-3D
Tools
Innovus, Tempus
Case study
RTL-to-GDSII Physical Design Flow Analysis
Comparative physical implementation across 10+ technology nodes.
GenusInnovusPrimeTimeTCL
Nodes
10+
Tools
Genus, Innovus, PrimeTime
Case study
Power Grid Optimization and IR Drop Analysis
Power-grid planning to keep IR drop ≤ 60 mV on 1.2 V VDD.
Cadence InnovusTCL
VDD
1.2 V
Max IR Drop
≤ 60 mV
Case study