Low-Power AES-128 Accelerator

Problem

Minimize leakage and dynamic power on an AES-128 block for always-on IoT, targeting < 50 µW @ 100 MHz.

Approach

• 01Multi-Vt synthesis: HVT in non-critical, SVT only where timing-critical.
• 02Power-gating using header switches with retention flops.
• 03Clock-gating density target > 95%.

Results

• → Total power 41 µW @ 100 MHz (18% under target).
• → Leakage reduced 62% vs. baseline.
• → Throughput 1.28 Gbps.

Screenshots