RISC-V Core — Full Physical Design

Problem

Implement an open-source RV32I core through the complete RTL-to-GDSII flow while closing timing at 1 GHz on the 45nm Nangate library.

Approach

• 01Floorplan: 350 µm × 350 µm, 70% utilization, IO ring with macro keep-outs.
• 02Power planning with dual-VDD straps and metal-9 mesh.
• 03CTS using H-tree clock topology — skew target < 50 ps.
• 04Routing with NDR on critical clock/data nets.
• 05Sign-off: PrimeTime ECO loop, Calibre DRC/LVS clean.

Results

• → WNS +0.02 ns @ 1.0 GHz worst-case (SS 0.81V 125°C).
• → Dynamic power reduced 12% via clock-gate insertion.
• → Zero DRC violations on final GDSII.

Screenshots

Reports