DINESH RAMCHARAN
BHUKYAVLSI Physical Design Engineer
M.Tech VLSI · Physical Design Engineer
Passionate VLSI Engineer specializing in Physical Design, Timing Analysis, RTL-to-GDSII implementation, and next-generation semiconductor technologies. Currently pursuing M.Tech at IIT Bhubaneswar while developing innovative solutions in chip design and optimization.
Engineering silicon from concept to closure
Semiconductor Technology & Chip Design postgraduate at IIT Bhubaneswar with strong foundations in Physical Design, Digital VLSI, ASIC Implementation, Static Timing Analysis and Semiconductor Engineering.
Professional Summary
I design, implement and optimize digital integrated circuits across the full RTL-to-GDSII flow. My research interests sit at the intersection of physical design automation, timing-driven optimization and emerging 3D IC architectures — translating algorithmic ideas into manufacturable silicon.
Interests
Education Timeline
M.Tech — Semiconductor Technology & Chip Design
Indian Institute of Technology, Bhubaneswar
Specialization in Physical Design, 3D ICs, advanced packaging & ASIC implementation.
B.Tech — Electronics & Communication Engineering
JNTUH UCES, Sulthanpur, Telangana
Foundations in digital design, VLSI, signal processing & embedded systems.
Intermediate (PCM)
TTWREIS SOE, Khammam
Physics, Chemistry & Mathematics — 76.4% — foundation for engineering studies.
Secondary School Certificate (10th)
Telangana Model School, Karepally
GPA: 8.8/10 — foundational schooling.
Real-world silicon experience
Industry exposure across RTL design, verification, synthesis and timing closure — combined with academic teaching impact.
VLSI Design Engineer Intern
Rudhaa Skillforge Technologies
- RTL design using Verilog
- SystemVerilog verification
- Simulation & synthesis flows
- Cadence and Vivado tool usage
- Static timing analysis
- Logic optimization
- HDL-based design development
Teaching Assistant
IIT Bhubaneswar
- Conducting lab sessions
- Tutorial guidance & problem-solving
- Evaluation of assignments & exams
- Mentoring undergraduate students
Selected work
Research projects spanning physical design automation, RTL design, analog IC design and hardware security.
Core competencies
Depth across physical design, HDL, EDA tools, scripting and semiconductor process.
Physical Design
HDL Design
EDA Tools
Programming
Semiconductor
The RTL-to-GDSII journey
An interactive walkthrough of every stage in the physical design flow. Click any node to learn more.
RTL Design
Hardware Description Language coding of digital logic in Verilog/SystemVerilog. Capture functionality and pass simulation-based verification.
Continuous learning
Curated technical certifications strengthening physical design, RTL and digital fundamentals.
VLSI Physical Design with Timing Analysis
NPTEL
VLSI Design — RTL to GDS
NPTEL
VLSI Digital Design — Chip Design & Verilog
Infosys Springboard
Design & Analysis of Digital Circuits
Alison
Digital Communication using GNU Radio
NPTEL
Digital Image Processing
NPTEL
VLSI for Beginners
NIELIT
VLSI SoC Design — Overview
Maven Silicon
Electronic & Micro-controller Circuit Design
Alison
Milestones along the silicon path
IIT Bhubaneswar M.Tech
Postgraduate in Semiconductor Technology & Chip Design.
VLSI Internship Experience
Industry exposure at Rudhaa Skillforge Technologies.
Semiconductor Research
Hands-on fabrication & device characterization.
Teaching Assistant
Mentoring & evaluation at IIT Bhubaneswar.
9+ VLSI Certifications
From NPTEL, Infosys, NIELIT & Maven Silicon.
10+ Projects Shipped
Across PD, RTL, analog & hardware security.
Let's build the next chip
Open to PD internships, full-time roles and research collaborations.