Notes from the trenches
Blog
VLSI, Physical Design, timing closure, and the occasional war story.
·8 min
RTL → GDSII in 7 Stages: A Practical Walkthrough
Synthesis, floorplan, placement, CTS, routing, sign-off, and tape-out — what really happens at each step.
PD FlowSynthesisPnR
·6 min
Closing Hold Violations Without Wrecking Setup
Why hold fixes are tricky, how useful-skew helps, and the buffer-insertion pitfalls to avoid.
TimingSTAECO
·7 min
Power-Aware Floorplanning for Sub-mW Designs
Voltage islands, retention strategies, and why your floorplan IS your power plan.
Low PowerFloorplanUPF