M.Tech VLSI · IIT Bhubaneswar · Physical Design Engineer
RTL-to-GDSII · Timing Closure (Setup/Hold) · Floorplanning · CTS · Routing · STA · Power Analysis · Innovus · Genus · PrimeTime · Calibre · Verilog · SystemVerilog · UPF · TCL · Python
RTL-to-GDSII implementation of a 5-stage RV32I core in 45nm.
Innovus · Genus · PrimeTime · Calibre · Verilog
Power-aware floorplanning + multi-Vt for IoT-class encryption.
Genus · Innovus · PrimeTime PX · Verilog
Sub-ps skew DLL + write-leveling on a 3200 MT/s PHY.
PrimeTime · Innovus · HSPICE
M.Tech, VLSI Design
Indian Institute of Technology Bhubaneswar · 2025–2027
Physical Design Internships & Full-Time Roles · Available immediately.