The RTL-to-GDSII journey is the heart of ASIC implementation. Every modern chip — from your AirPods' H2 to NVIDIA's H100 — goes through some flavor of these seven stages.
1. Logic Synthesis
Genus or Design Compiler maps your Verilog into a gate-level netlist against a target library. Constraints (SDC) define the rules: clocks, IO delays, false paths.
2. Floorplan
Decide die size, macro placement, IO ring, power straps. Get this wrong and no amount of clever placement will save you.
3. Placement
Standard cells are placed to minimize wirelength while respecting timing and density. Innovus uses an analytical placer with congestion-aware refinement.
4. CTS
Clock Tree Synthesis builds a balanced tree to minimize skew. H-trees and multi-source CTS are common. Target skew < 50 ps for high-frequency designs.
5. Routing
Global + detailed routing connects every net. NDR (non-default rules) protect critical signals from coupling.
6. Sign-off
STA across PVT corners (PrimeTime), DRC/LVS (Calibre), IR-drop (Voltus). One missed corner = a respin.
7. Tape-out
GDSII to the foundry. Months of fabrication later — silicon.