SHA256 Physical Design Implementation

Problem

Implement a SHA256 digital design through the complete RTL-to-GDSII physical design flow using Cadence Innovus with the ASAP7nm technology library.

Approach

• 01Floorplanning, tap-cell insertion, I/O pin placement, and power-ring/stripe/rail generation via TCL-based Innovus scripts.
• 02Standard-cell placement with placeOptDesign and PPA reporting for area, power, timing, placement density, and routing quality.
• 03Clock tree synthesis and detailed signal routing, investigating metal-spacing, shorts, and congestion-related issues.
• 04Post-route timing, power, and area analysis using report timing, report power, report area, and optDesign.

Results

• → Full placement and routing flow completed in ASAP7nm.
• → Post-route timing and power reports generated.
• → Routing and DRC violations identified and tracked for closure.

Screenshots

Reports