RTL-to-GDSII Physical Design Flow Analysis

Problem

Explore the complete RTL-to-GDSII implementation flow including synthesis, floorplanning, placement, CTS, routing, and timing analysis across a wide range of technology nodes.

Approach

• 01Complete RTL-to-GDSII implementation across multiple technology environments including ASAP7, 5nm, 7nm, 10nm, 16nm, 20nm, 45nm, 90nm, 180nm, and 3D PDK designs.
• 02Synthesis, floorplanning, placement, CTS, routing, and sign-off analysis using Genus and Innovus.
• 03Post-implementation timing analysis using PrimeTime, investigating critical paths, setup/hold violations, and timing optimization techniques.

Results

• → Hands-on implementation experience across 10+ advanced technology nodes.
• → Critical path and setup/hold violation analysis using PrimeTime.
• → Comparative understanding of node-specific design constraints.

Screenshots

Reports