Automated 3D IC Compiler Flow for Simultaneous Timing Closure

Problem

Develop an automated pseudo-3D physical design flow that enables existing 2D EDA engines to perform timing-aware implementation of multi-tier 3D IC designs.

Approach

• 01Timing-aware tier partitioning and pseudo-3D floorplanning, placement, CTS, routing, and timing closure using Cadence Innovus and Tempus.
• 02TCL automation scripts and modified SDC constraints to represent 3D inter-tier connections using anchor-cell abstractions.
• 03Evaluation of Compact-2D and Cascade-2D implementation strategies for concurrent placement, CTS, routing, and timing optimization.

Results

• → Pseudo-3D flow architecture enabling 2D EDA reuse for 3D ICs.
• → Anchor-cell abstraction for inter-tier netlist connectivity.
• → Framework for simultaneous multi-tier timing closure.

Screenshots

Reports